IEC TS 62804-1-2015 PDF

Full title and description

Photovoltaic (PV) modules - Test methods for the detection of potential‑induced degradation - Part 1: Crystalline silicon. IEC TS 62804-1:2015 defines procedures to test and evaluate the durability of crystalline silicon PV modules when exposed to short‑term high‑voltage stress that can cause potential‑induced degradation (PID). Two screening test methods are specified to achieve a controlled stress level and assess module sensitivity to PID mechanisms that involve mobile ions and electric field effects on the silicon semiconductor.

Abstract

This Technical Specification provides standardized chamber test procedures to detect and characterise potential‑induced degradation in crystalline silicon PV modules. It describes two accelerated screening tests (not necessarily equivalent) intended to reveal module sensitivity to system voltage stress under controlled conditions. The methods are aimed at modules with one or two glass surfaces and cells with passivating dielectric layers; they are not intended to cover all field factors or thin‑film technologies.

General information

• Status: Withdrawn (revised by IEC TS 62804-1:2025; withdrawal effective 13 June 2025).
• Publication date: 6 August 2015.
• Publisher: International Electrotechnical Commission (IEC).
• ICS / categories: 27.160 (Solar energy engineering).
• Edition / version: Edition 1.0 (2015).
• Number of pages: 15 pages.

Scope

IEC TS 62804-1:2015 defines apparatus, procedures and acceptance concepts for short‑term accelerated tests to detect potential‑induced degradation (PID) in crystalline silicon PV modules. The document is intended for modules with one or two glass surfaces and silicon cells that include passivating dielectric layers; it addresses degradation mechanisms arising from mobile ions or electronic interactions that modify the electric field over the semiconductor. The specification provides screening tests (two methods) to assess module sensitivity but does not attempt to reproduce every environmental factor present in field operation and is not intended for thin‑film, tandem or heterojunction devices.

Key topics and requirements

• Definition of two accelerated screening test methods to reveal PID susceptibility in crystalline silicon modules (constant stress level control, test durations and pass/fail assessment criteria).
• Test apparatus and electrical biasing arrangements to apply high voltage stress to the active circuit relative to ground.
• Guidance on sample selection, conditioning and measurement of power/IV before and after stress.
• Limitations and applicability: designed for modules with passivating dielectric layers; not a full replication of outdoor conditions and not intended for thin‑film technologies.
• Normative references and cross‑references to environmental and qualification standards used in conjunction with PID testing.

Typical use and users

Used by PV module manufacturers, third‑party test laboratories, certification bodies, research groups and reliability engineers to screen crystalline silicon module designs for sensitivity to potential‑induced degradation. Procurement teams and quality managers may reference the tests to compare module PID resistance during design qualification and supplier evaluation.

Related standards

Commonly used alongside or referenced with other IEC and test standards for PV qualification and environmental testing, including IEC 61215 (design qualification for crystalline silicon modules), IEC 61730 (safety of PV modules), IEC 60068‑2‑78 (damp heat testing) and IEC 60410 (sampling procedures). The 2015 Technical Specification has later related parts and revisions (see IEC TS 62804‑2 for thin‑film and IEC TS 62804‑1:2025 for a revised Part 1).

Keywords

potential‑induced degradation; PID; photovoltaic modules; crystalline silicon; accelerated testing; PV reliability; voltage stress; IEC TS 62804‑1.

FAQ

Q: What is this standard?

A: IEC TS 62804‑1:2015 is a technical specification that defines chamber test procedures to detect potential‑induced degradation (PID) in crystalline silicon photovoltaic (PV) modules.

Q: What does it cover?

A: It covers two accelerated screening test methods, the required biasing arrangements, sample handling and measurement approaches to identify module sensitivity to PID mechanisms (principally those involving mobile ions and electric‑field effects on silicon cells). It is focused on crystalline silicon modules with passivating dielectric layers and is not intended to replicate all field conditions.

Q: Who typically uses it?

A: Module manufacturers, independent test laboratories, certification bodies, PV system designers and reliability engineers use the specification to screen and compare crystalline silicon module designs for PID susceptibility.

Q: Is it current or superseded?

A: The 2015 edition (Edition 1.0) was published 6 August 2015 and has been revised — IEC TS 62804‑1:2025 is the later revision; the 2015 Technical Specification was withdrawn with effect 13 June 2025 when the 2025 edition was published. Users should refer to IEC TS 62804‑1:2025 for the most up‑to‑date procedures and additional test variations.

Q: Is it part of a series?

A: Yes. IEC TS 62804 has multiple parts: Part 1 addresses crystalline silicon modules (original 2015 edition, revised 2025), and a separate Part 2 covers thin‑film module PID test methods (published as IEC TS 62804‑2:2022). Practitioners evaluating different PV technologies should consult the appropriate part for their technology.

Q: What are the key keywords?

A: Potential‑induced degradation (PID), PV modules, crystalline silicon, accelerated test methods, voltage bias, damp heat, passivating dielectric layers, screening tests.