IEC PAS 62162-2000 PDF

Full title and description

IEC/PAS 62162:2000 — Field‑induced charged‑device model (CDM) test method for electrostatic discharge (ESD) withstand thresholds of microelectronic components. Describes a uniform laboratory method and associated test circuitry, waveform verification and measurement procedures for determining CDM ESD withstand thresholds of packaged semiconductor devices, thin‑film circuits, SAW components, opto‑electronic devices, hybrid ICs and multi‑chip modules (and similar assemblies).

Abstract

This Publicly Available Specification defines the field‑induced CDM simulator, required waveform characteristics, measurement instrumentation and test sequence used to establish CDM ESD withstand levels for microelectronic components. It also sets voltage levels, test procedures and failure criteria to ensure repeatable component classification and comparison across test laboratories. The PAS was subsequently reissued/replaced by full IEC standards addressing semiconductor ESD test methods.

General information

• Status: Replaced / superseded. IEC records show the PAS has been replaced by a subsequent IEC standard (see IEC 60749‑28:2017 as the successor); the PAS was marked withdrawn in IEC catalogues (withdrawal recorded 28 March 2017) and later removed from some national catalogues.
• Publication date: 22 August 2000 (Edition 1.0).
• Publisher: International Electrotechnical Commission (IEC).
• ICS / categories: 31.080.01 (Semiconductor devices in general; quality assurance / ESD testing).
• Edition / version: Edition 1.0 (IEC/PAS 62162:2000).
• Number of pages: 7 pages (IEC catalogue listing).

Scope

The PAS specifies a field‑induced charged‑device model test method to determine ESD withstand thresholds of microelectronic components and packages. It applies to packaged semiconductor components, thin‑film circuits, surface acoustic wave (SAW) components, opto‑electronic components, hybrid integrated circuits (HICs) and multi‑chip modules (MCMs); it may also be applied to bare dies or wafers if assembled into a representative package for the test. The document covers simulator circuitry, waveform verification, instrumentation, voltage selection and failure criteria to produce reproducible CDM threshold data.

Key topics and requirements

• Definition and purpose of the field‑induced charged‑device model (CDM) for component‑level ESD assessment.
• Detailed circuit schematic and construction requirements for a CDM simulator (field‑induced type).
• Waveform verification procedures, waveform characteristics and allowable tolerances.
• Measurement instrumentation, probes and monitoring arrangements needed to capture CDM events.
• Specified voltage levels and step sequences for determining withstand thresholds and classification.
• Pass/fail criteria and reporting requirements for ESD‑induced failures.
• Applicability notes for testing packaged parts vs. bare dies, and requirements to record package type and handling.

Typical use and users

Used by semiconductor manufacturers, device qualification and reliability engineers, independent test laboratories, ESD/quality assurance teams and OEM test engineers to classify device CDM robustness, compare products and set handling/assembly precautions. It's also referenced by test‑equipment vendors and standards committees when aligning laboratory methods for device‑level ESD testing.

Related standards

Directly related and successor documents include IEC 60749‑28 (the IEC published standard that superseded the PAS) and other IEC/JEDEC ESD test method publications; JEDEC field‑induced CDM test methods (JEDEC/JESD references) are closely associated. System‑level immunity standards (for example IEC 61000‑4‑2) cover different ESD scopes and are complementary rather than equivalent.

Keywords

ESD, CDM, charged‑device model, electrostatic discharge, microelectronic components, semiconductor testing, CDM simulator, waveform verification, ESD withstand threshold, package testing.

FAQ

Q: What is this standard?

A: IEC/PAS 62162:2000 is a Publicly Available Specification that defines a field‑induced charged‑device model (CDM) test method for determining electrostatic discharge (ESD) withstand thresholds of microelectronic components.

Q: What does it cover?

A: It covers the CDM simulator circuit, waveform characteristics and verification, measurement instrumentation and procedures, voltage levels and failure criteria required to obtain reproducible CDM ESD threshold data for packaged semiconductors and similar components.

Q: Who typically uses it?

A: Semiconductor manufacturers, device qualification and reliability engineers, independent test houses, ESD/quality teams, OEM test laboratories and test‑equipment suppliers.

Q: Is it current or superseded?

A: It has been superseded/replaced. IEC catalog records indicate the PAS was withdrawn from the IEC catalogue and replaced by later IEC standards addressing CDM/ESD testing (IEC 60749‑28 and related IEC/JEDEC documents are the successors). IEC lists a withdrawal/replacement action (withdrawal recorded 28 March 2017 in the IEC catalogue) while some national catalogues reflect later removal dates; users should consult the current IEC/ national catalogue or the successor standard (IEC 60749‑28:2017) for the up‑to‑date test method.

Q: Is it part of a series?

A: Yes — the PAS was developed by IEC TC 47 (Semiconductor devices) and is part of the family of IEC/JEDEC test methods for semiconductor device ESD and reliability testing; its content was folded into subsequent IEC standards in the semiconductor testing series (see IEC 60749‑28 and related IEC/JEDEC documents).

Q: What are the key keywords?

A: Charged‑Device Model (CDM), electrostatic discharge (ESD), test method, withstand threshold, semiconductor, package testing, waveform verification.